1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device carrying out data input/output in a predetermined bit organization out of a plurality of bit organizations.
2. Description of the Background Art
Semiconductor devices are now used in various types of equipments. Semiconductor memory devices are developed that can have the input/output unit of data, i.e. the bit organization, selected, according to the needs of the user for the sake of consistency with the device to be used. Such a semiconductor memory device is disclosed in Japanese Patent Laying-Open No. 64-73597.
This conventional semiconductor memory device will be described hereinafter with reference to the block diagram of FIG. 18.
Referring to FIG. 18, a semiconductor memory device includes a refresh address counter RCTR, a row address buffer RADB, a column address buffer CADB, a nibble counter NCTR, a prerow address decoder PRDCR, a redundant address select circuit RAC, a precolumn address decoder PCDCR, an address signal change detection circuit ATD, a timing generation circuit TG, row address decoders RDCR0-RDCR3, N type sense amplifiers SAN0-SAN3, memory arrays MARY0-MARY3, P type sense amplifiers SAP0-SAP3, column switches CS0-CS3, column address decoders CDCR0-CDCR3, main amplifiers MA0-MA7, test logic circuit TL, data output buffers DOB1-DOB4, data input buffers DIB1-DIB4, and a voltage generation circuit VG.
The semiconductor device of the above-described structure amplifies data stored in a predetermined memory cell of memory arrays MARY0-MARY3 specified by an address signal by main amplifiers MA0-MA7 to provide the amplified data to test logic circuit TL and data output buffers DOB1-DOB4.
Data output buffers DOB1-DOB4 and test logic circuit TL will be described in detail hereinafter with reference to FIG. 19 showing the structure of the data output buffer and the test logic circuit of FIG. 18.
Data is read out to an I/O line from a memory cell selected by a row address signal and a column address signal. The data read out to the I/O line is amplified by main amplifiers MA0-MA7 to be provided to a data bus. In the above-described conventional semiconductor memory device, a bit organization of x1 bit or x4 bits can be selected by selectively using different types of photomasks created in advance. In either case of a x1 organization or a x4 bit organization, output signals MO1-M03, /M00-/M03 ("/" indicates an inverting signal) of main amplifiers MA0-MA3 are simultaneously output as 4 bits to be input to respective data output buffers DOB1-DOB4.
In a x4 bit organization, output signals MO0-M03 and /MO0-/MO3 are provided to respective data output buffers DOB1-DOB4, whereby 4 bits of output data D1-D4 are output.
In a x1 bit organization, one complementary signal out of the four complementary signals MO0-M03,/MO0-/M03 is selected by address signals AXY0-AXY3 which are entered to test logic circuit TL. The selected complementary signal is provided to data output buffer DOB3. Data output buffer DOB3 outputs data of 1 bit from the input complementary signal.
Test logic circuit TL functions to test the match/mismatch of the read out data of 4 bits. When a test mode signal TE attains a H level (high potential), signals mp0-mp3 attain a H level simultaneously by signal DS irrespective of address signals AXY0-AXY3. When signals mp0-mp3 attain a H level, output signals MO0-M03, /MO0-/M03 of main amplifiers MA0-MA3 are provided to respective 4-input NAND gates. When all the data of 4 bits read out from memory cell array MARY0-MARY1 attain a H level, all output signals MO0-M03 and/MO0-/M03 attain a H level and a L level (ground potential), respectively. Therefore, a signal of a L level is output from a data output pad D.sub.out. When all the read out data of 4 bits attain a L level, output signals MO0-M03 and/MO0-/M03 attain a L level and a H level, respectively. Therefore, a signal of a H level is output from data output pad D.sub.out. When at least 1 different data bit of the 4 bits of data is read out, the output of the 4 NAND gate to which output signals MO0-M03 are input and the output of the 4 NAND gate to which output signals/MO0-/M03 are input all attain a H level, whereby data output pad D.sub.out attains a high impedance state. Thus, when test mode signal TE receives a H level signal, match/mismatch of the 4 bits of data read out from memory cell arrays MARY0-MARY1 can be detected.
As described above, a conventional semiconductor memory device can be selectively produced to employ a x1 bit organization or a x4 bit organization by partially modifying the photomask to meet the needs of the user.
A conventional semiconductor memory device amplifies data read out from a memory cell with a main amplifier, whereby the amplified data is input to a data output buffer and a test logic circuit via a data bus. All the read out data in the x1 bit organization and the x4 bit organization is transferred via a data bus, so that the access time was determined by the data bus of the longest transfer time period when the data buses have different transmission time periods. This means that an unrequired data bus is used in a 1 bit organization and the access time is dependent upon by the data bus having the longest data transmission time. There was the problem that access required a longer time.
Because all the data buses are used, there was also a problem that power consumption is increased due to charge/discharge of unrequired data buses.